1. Field of the Invention
The present invention relates to a step-up circuit for stepping up an external power supply voltage that is supplied from outside, and particularly to a charge pump circuit that generates a stepped-up voltage that is applied to the word lines of a semiconductor memory device, and to a step-up circuit that is provided with such a charge pump circuit.
2. Description of the Related Art
In recent years, semiconductor integrated circuit devices such as semiconductor memory devices do not only use external power supply voltage V.sub.CC supplied from outside as is, but rather, in the interest of promoting low power consumption and improving element reliability, step down or step up voltage to generate a prescribed internal power supply voltage which is then supplied to each of the necessary internal circuits.
As a semiconductor integrated circuit device with necessitating this type of internal power supply voltage, DRAM (Dynamic Random Access Memory), for example, typically has a configuration that includes a storage capacitor that stores information by storing a signal charge in a memory cell and a switching transistor for controlling the storage/discharge of the signal charge in the storage capacitor, an n-channel MOS field effect transistor (hereinbelow referred to as a "NMOS transistor") being used as the switching transistor.
The switching transistor has its drain connected to a bit line, its gate connected to a word line, and its source connected to ground by way of the storage capacitor, and the transistor cannot be turned ON unless a voltage is applied to the gate that is higher than the source voltage by a threshold voltage V.sub.TH. The source voltage normally varies between 0 and V.sub.CC, so a voltage of at least (V.sub.CC +V.sub.TH) must be applied to the gate to turn ON the switching transistor. A step-up circuit that steps up the external power supply voltage V.sub.CC generates a stepped-up voltage that is applied to the gate (word line) of the switching transistor.
The voltage endurance of transistors used in semiconductor integrated devices in recent years, however, has tended to decrease with miniaturization. The power supply voltage must consequently be decreased, but in the interest of providing a power supply that is shared with other logic circuits composed of TTL (Transistor-Transistor Logic), a configuration is adopted in which an external power supply voltage V.sub.CC is stepped down by a step-down power supply circuit provided inside the chip, this stepped-down voltage then being supplied to the necessary internal circuits.
For example, if external power supply voltage V.sub.CC is made 5 V, the internal power supply voltage that is supplied to internal circuits requiring a stepped-down voltage is stepped down to 3.3 V by a step-down power supply circuit. Despite miniaturization of the transistor size, the threshold voltage V.sub.TH of transistors is not necessarily scaled down as is the power supply voltage.
In semiconductor integrated circuit devices, burn-in tests are commonly carried out after fabrication to eliminate initial defects. In a burn-in test, a voltage that is higher than the normal external power supply voltage V.sub.CC is applied to the semiconductor integrated circuit that is under test. In DRAM, the substrate is biased to a negative voltage to improve charge-holding characteristics, and in such a case, a voltage which is the sum of the negative voltage to the substrate added to the step-up voltage is applied to transistors used in the step-up circuit. Breakdown may occur when a voltage that exceeds the junction voltage endurance is applied.
In Japanese Patent Laid-open No. 140889/94 (hereinbelow referred to as "the first example of the prior art"), a semiconductor device is proposed that is provided with a clamping circuit that clamps the stepped-up voltage and a clamping control means for allowing change of this clamped voltage, thereby preventing junction breakdown of transistors within the step-up circuit by changing the clamped voltage used during normal operation and during a burn-in test.
In the semiconductor device described in the first example of the prior art, the step-up circuit is caused to operate only when high voltage is necessary (for example, during memory access), and when high voltage is not necessary, the output of the step-up circuit is connected to a ground potential line by the clamping circuit, whereby the voltage of the stepped-up voltage line for supplying stepped-up voltage to internal circuits is made to equal the ground potential.
Since parasitic capacitance is present in a stepped-up voltage line of this type of configuration, the step-up circuit charges the parasitic capacitance of the stepped-up voltage line each time the memory is accessed, and the electric charge of the parasitic capacitance of the stepped-up voltage lines that has been stored must then be discharged each time access is completed. In particular, stepped-up voltage lines have become longer with the increase in memory capacitance in semiconductor memory devices of recent years, thereby resulting in a trend toward an even greater parasitic capacitance and a consequent increase in the current consumed by a step-up circuit.
In addition, because the charge that has been stored in the parasitic capacitance of the stepped-up voltage lines is discharged by the clamping circuit, the loss current by the clamping circuit results in greater consumption of current by the step-up circuit. The high current consumption of the step-up circuit of the first example of the prior art as described hereinabove necessitates transistors having high current supply capabilities, and a greater loss current therefore flows to the clamping circuit than in the second example of the prior art, to be described hereinbelow.
When accessing memory, the charging of the stepped-up voltage lines when the step-up circuit is first operated lengthens the time for the voltage of the word lines that are connected to the stepped-up voltage lines to reach a prescribed value, and the speed of reading and writing information therefore drops. In order to make the voltage of the stepped-up voltage lines reach the prescribed value in a shorter time, the capacitance of a step-up capacitor should be made greater than the parasitic capacitance of the stepped-up voltage lines. When the capacitance of the capacitor is increased, however, the chip area also increased.
To solve the above-described problem of the first example of the prior art, Japanese Patent Laid-open No. 153493/94 (hereinbelow referred to as the "second example of the prior art) proposes a configuration in which a stepped-up voltage is always outputted and a control circuit turns the connection of the step-up circuit output and word lines ON and OFF.
Since the stepped-up voltage lines are always charged in the configuration of the second example of the prior art, the consumption of power that accompanies the charge and discharge of the stepped-up voltage lines can be suppressed and the rise time of the voltage of the word lines is not delayed. In addition, the chip area is not increased because there is no need to increase the capacitance of the step-up capacitor.
In addition, the provision of a limiting circuit for limiting the stepped-up voltage and a step-up clock voltage control circuit for limiting the output amplitude of a clock driver for driving a step-up clock in the second example of the prior art allows a decrease in the power consumption of the step-up circuit that includes a limiting circuit.
Nevertheless, the use of MOS transistors having drains and gates connected together as a diode for rectifying the step-up clock in the second example of the prior art results in the problems of large voltage drops due to the diode, poor rectifying efficiency, and inability to obtain the desired step-up voltage.
Japanese Patent Laid-open No. 14529/94 (hereinbelow referred to as the "third example of the prior art") proposes a step-up circuit that improves rectifying efficiency by not connecting transistors as diodes as in the second example of the prior art, but rather, by switch-operating the transistors as shown in FIG. 1.
In FIG. 1, the charge pump circuit of the step-up circuit of the third example of the prior art carries out multiple-voltage rectification by clocks .phi..sub.A, .phi..sub.B, and .phi..sub.C and generates a stepped-up voltage, and includes: first inverter 101 that inverts clock .phi..sub.A composed of a prescribed cycle and outputs the result at amplitude of external power supply voltage V.sub.CC ; second inverter 102 that inverts clock .phi..sub.B composed of a prescribed cycle and outputs the result at amplitude of external power supply voltage V.sub.CC ; third inverter 103 that inverts clock .phi..sub.C composed of a prescribed cycle and outputs the result at amplitude of stepped-up voltage V.sub.BOOT ; step-up capacitors C1, C2, and C3 that are connected to the output ends of first through third inverters 101-103, respectively; NMOS transistor Q1 that receives the output clock of step-up capacitor C1, turns ON and OFF in accordance with the output clock of step-up capacitor C3, and outputs stepped-up voltage V.sub.BOOT that is higher than external power supply voltage V.sub.CC that is supplied from outside; NMOS transistor Q2 for biasing the output voltage of step-up capacitor C1 by external power supply voltage V.sub.CC and that turns ON and OFF in accordance with the output clock of step-up capacitor C2; NMOS transistor Q3 for biasing the output voltage of step-up capacitor C3 by external power supply voltage V.sub.CC and that turns ON and OFF in accordance with the output clock of step-up capacitor C2; and NMOS transistor Q4 for biasing the output voltage of step-up capacitor C2 by external power supply voltage V.sub.CC and that turns ON and OFF in accordance with the output clock of step-up capacitor C3. First inverter 101 is made up by p-channel transistor P1 and n-channel transistor N1, second inverter 102 by p-channel transistor P2 and n-channel transistor N2, and third inverter 103 by p-channel transistor P3 and n-channel transistor N3. The block made up by transistors Q1 and Q2 and step-up capacitor C1 is step-up section 111, and the block made up of transistors Q3 and Q4 and step-up capacitors C2 and C3 is step-up control unit 112.
The operation of the charge pump circuit of the third example of the prior art shown in FIG. 1 is next explained using FIG. 2 and FIG. 3. FIG. 3 shows the maximum voltages generated at nodes A, B, and C with respect to changes in the external power supply voltage of the charge pump circuit shown in FIG. 1, and voltage V.sub.BOOT of node D shows the set value. Voltage V.sub.BOOT of node D is smoothed by a load capacitance (not shown in the figures) and controlled by a judging circuit (not shown) to equal the set value, and voltage V.sub.BOOT is therefore maintained at substantially the set value voltage when the power supply voltage is greater than voltage V.sub.1. In addition, although the duty ratios of clocks .phi..sub.B and .phi..sub.C are described as being 50% (i.e., clocks .phi..sub.B and .phi..sub.C rise and fall simultaneously with the rise and fall of clock .phi..sub.A) in the following explanation, in actual practice, the duty ratios of clocks .phi..sub.B and .phi..sub.C are set to 50% or less to prevent short-circuit currents.
First, as shown in FIG. 2, when clocks .phi..sub.A and .phi..sub.C are at high level and clock .phi..sub.B is at low level at time t.sub.0, the outputs of first inverter 101 and third inverter 103 become low level and the output of second inverter 102 becomes high level. At this time, transistors Q2, Q3, N1, P1, and N3 each turn ON, and transistors Q1, Q4, P1, N2, and P3 each turn OFF.
The high-level output voltage of second inverter 102 is thus added to capacitor C2 that was charged by the power supply voltage (hereinbelow referred to as "V.sub.CC ") and the voltage of node B becomes 2V.sub.CC. The voltage of node A drops for an instant because the first inverter 101 end of capacitor C1 is discharged to a low level, but when the voltage of node B 2V.sub.CC is supplied to the gate of transistor Q2, transistor Q2 turns ON and node A is gradually charged to V.sub.CC.
In the same way, transistors Q3 and N3 each turn ON, which causes the node C side of capacitor C3 to be charged to stepped-up voltage V.sub.BOOT, which is the output of the charge pump circuit, and the other end of capacitor C3 is discharged to the ground potential.
Next, at time t.sub.1, clocks .phi..sub.A and .phi..sub.C switch to low level and clock .phi..sub.B switches to high level, whereupon the outputs of first inverter 101 and third inverter 103 become high level and the output of second inverter 102 becomes low level. At this time, transistors Q2, Q3, N1, P1, and N3 each turn OFF, and transistors Q1, Q4, P1, N2, and P3 each turn ON.
Accordingly, the high-level output voltage of inverter 103 is added to capacitor C3, which was charged to V.sub.BOOT, and the voltage of node C becomes V.sub.CC +V.sub.BOOT. In addition, the voltage of node A becomes 2V.sub.CC because the first inverter 101 end of capacitor C1 is charged to V.sub.CC, and this V.sub.CC is added to the voltage of node A, which was V.sub.CC until this point. When the voltage of node C becomes V.sub.CC +V.sub.BOOT and this voltage is supplied to the gate of transistor Q1, transistor Q1 turns ON and 2V.sub.CC is outputted from node D as stepped-up voltage V.sub.BOOT.
Next, the charge that was stored in capacitor C1 is discharged and the voltage of node A gradually drops from 2V.sub.CC, whereupon transistors Q4 and N2 turn ON, causing the node B side of capacitor C2 to be charged to V.sub.CC and the other end to be discharged to the ground potential. The operation of times t.sub.0 and t.sub.1 are subsequently repeated in the same way, and the stepped-up voltage V.sub.BOOT continues to be outputted from the charge pump circuit.
The stepped-up voltage V.sub.BOOT is supplied to the source of the p-channel transistor of third inverter 103 for the following reason.
Transistor Q1 is an NMOS transistor, the drain of which is connected to node A, and a voltage stepped-up to 2V.sub.CC is supplied at time t.sub.1. If 2V.sub.CC is supplied to the gate of transistor Q1 and transistor Q1 is turned ON, the source voltage is normally lower than the gate voltage by just the threshold voltage V.sub.TH. A stepped-up voltage of 2V.sub.CC -V.sub.TH is therefore outputted from the source of transistor Q1, and the step-up efficiency is decreased by the occurrence of the threshold voltage V.sub.TH loss. To decrease this type of loss, the voltage supplied to the gate of transistor Q1 should be a voltage of at least 2V.sub.CC +V.sub.TH, and this voltage is generated in the third example of the prior art by supplying stepped-up voltage V.sub.BOOT to third inverter 103.
As shown in FIG. 2, in the charge pump circuit according to the third example of the prior art, a voltage of 2V.sub.CC is supplied to the source or drain of NMOS transistor Q1 that is connected to node A and the gate of NMOS transistor Q2 that is connected to node B, and a voltage of (V.sub.CC +V.sub.BOOT) is supplied to the gate of NMOS transistor Q1 that is connected to node C.
In the charge pump circuit according to the third example of the prior art, when the power supply voltage V.sub.CC increases, nodes A and B also increase proportionally, as shown in FIG. 3. In contrast, node D increases in proportion to V.sub.CC until power supply voltage V.sub.CC reaches V.sub.1 but then remains constant when power supply voltage V.sub.CC is within the range V.sub.1 -V.sub.2. This constant value for node D is obtained because the semiconductor integrated circuit is being used within the range of power supply voltage V.sub.1 -V.sub.2 (hereinbelow referred to as "normal operating voltage"), and within this normal operating voltage, stepped-up voltage V.sub.BOOT is controlled to a constant by a stabilizing means (not shown in the figures) such that the performance of the semiconductor integrated circuit is not dependent on fluctuations in the power supply voltage. When the power supply voltage exceeds V.sub.2, the stabilizing means uses a voltage that is resistance-divided from power supply voltage V.sub.CC as a control reference voltage, and node D again increases in proportion to V.sub.CC, although with a more gradual inclination than the inclination up to V.sub.1. Variation at node C also changes in accordance with the change at node D.
Stepped-up voltage V.sub.BOOT is thus suppressed to a prescribed range at a normal operating voltage, but accelerated tests, such as in burn-in tests, are commonly performed in which a voltage higher than the normal operating voltage is supplied to internal circuits to quickly and efficiently eliminate initial defects.
As described hereinabove, there has been a trend in recent years for the voltage endurance of transistors used in semiconductor integrated circuits to decrease with miniaturization, and when a voltage of 2V.sub.CC or V.sub.BOOT +V.sub.CC is applied to the source or drain of a transistor, a leak current flows from the diffusion layer of the source or drain to the semiconductor substrate or well region, and in a worst case, breakdown occurs in the junction area of the diffusion layer.
In a case in which a charge pump circuit such as shown in FIG. 1 is constructed of transistors having a semiconductor substrate potential of 0 V and a junction voltage endurance of 10 V, for example, if the normal operating voltage V.sub.2 is 3.6 V and the stabilized stepped-up voltage V.sub.BOOT is 4.5 V, nodes A and B will experience a maximum voltage of 7.2 V and node C will experience a maximum voltage of 8.1 V. The voltage will thus remain within the junction voltage endurance of the transistor during normal operation and the semiconductor integrated circuit will operate without problem.
If a voltage of 5 V is supplied as the external power supply voltage V.sub.CC during a burn-in test, however, a voltage of 10 V+.alpha. will be supplied to the drain of NMOS transistor Q3 that is connected to node C, a leak current will flow from the transistor drain toward the substrate, and breakdown will occur in the junction region of the diffusion layer.
The well region is generally biased to about -1.5 V to prevent the loss of a signal charge stored in the capacitor of a memory cell region due to, for example, noise. In a semiconductor memory device in which manufacturing steps have been reduced by eliminating well regions, memory cell regions and peripheral circuit regions are formed in the same well regions, and the voltage of these well regions, moreover, is set to the same level. A voltage of 11.5 V is therefore applied to the drain of NMOS transistor Q4 that is connected to node B and a voltage of 11.5 V+.alpha. is applied to the drain of NMOS transistor Q3 that is connected to node C, thus increasing the possibility of the occurrence of a leak current and the destruction of the junction portion.
Even though the breakdown may not occur in the junction portion, the flow of a leak current between the semiconductor substrate and the source or drain of a transistor causes the voltage of the well region to rise. Since the sources and drains of transistors provided in the memory cell region are biased in the forward direction with respect to the voltage of the well region, the signal charge stored in storage capacitors is instantly discharged and the stored information vanishes.
Although these problems can be solved by raising the junction voltage endurance of the transistor, the impurity concentration of the diffusion layer that makes up the source and drain must be made lower than in other transistors, and this necessitates the preparation of separate masks and additional processes. These additional masks and procedures raise the costs of the semiconductor integrated circuit. In addition, the size of the transistor increases, and this also raises chip area and the base cost of the chip.